Position: Postdoctoral Scholar
Current Institution: UC San Diego
Abstract: Microarchitectural Prediction for Performance and Security
My research focuses on microarchitectural prediction for performance and security in hardware [GHRP-ISCA2018 BLBP-ISCA2019 CHIRP-MICRO2020 PerSpectron-MICRO2020 SubmittedForPublication-A2021]. I extended this line of research with improving hardware-detectors using GANs (generative-adversarial-networks) to pre-harden them against evasive-attacks [SubmittedForPublication-B2021]. My current research also analyzes vulnerabilities related to data-leakage through various predictive-metadata in the processor. This work will show in a systematic way that most metadata used in various predictive-units (replacement-policies prefetchers cache-coherency-protocols store-to-load-forwarding etc.) are subject to leakage. It will disclose a new design using secret-agnostic-metadata that isolates learning across protection-domains while improving prediction performance. My prior work showed that lightweight hardware machine-learning structures could be highly effective at diagnosing microarchitectural security attacks [PerSpectron-MICRO2020]. My future work opens the door to a much broader and to this point unexploited opportunity to use lightweight ML in hardware to diagnose a wide spectrum of microarchitectural problems and anomalies that provides security mitigations which can not be done in software. Data analysis from my prior work revealed an interesting phenomenon: many microarchitectural-features correlated to attacks also correlate with events related to performance. I exploit this phenomenon merging performance and security in hardware by proposing an end-to-end strategy for defending systems and monitoring performance bottlenecks simultaneously. As the microarchitectural-signatures of each attack manifest in different pipeline-components we can enable suitable and satisfactory countermeasures to close the attack surface completely prior-to-leakage as well as diagnosing performance-and-power bottlenecks. This could include bottlenecks in control-flow prediction structures (branch-predictors BTB) front-end caching and other specialized structures (uop-cache LSD iTLB etc.) instruction window structures (reservation-stations ROB renaming-registers load-store queues etc.) other structural hazards (execution-ports fetch and decode bandwidth etc.) or caches triggering instant transformations in software or hardware to improve performance. This will ultimately result in a ground up redesign of computer architecture optimizations for security and performance utilizing machine learning in hardware.
Samira Mirbagher-Ajorpaz is a postdoctoral scholar and UC Fellow in the Computer Science Department at the University of California San Diego. Before this she was a postdoctoral researcher at Texas A&M University where she also received her PhD in Computer Science. She is interested in making computation faster and more secure. Her focus is on microarchitecture and designing prediction units with small-scale and tight-time margins. She is also drawn to teaching leadership and service roles in her university and research communities. She served on the Program-Committee of top-tier conferences in computer-architecture. She taught advanced-machine-learning and advanced-micro-architecture at Texas-A&M and UC San-Diego. Her recent publication on improving Virtual-Address-Translation was selected for the IEEE-Lance-Stafford-Larson Award 2021. She published multiple papers in ISCA as well as two first-author papers simultaneously in MICRO. She is known for inventing the PerSpectron microarchitectural level detection of speculative attacks which is currently being prototyped by industry.